1. Field of the Invention
The present invention relates generally to computer systems. More particularly, the present invention relates to microprocessors and compilers.
2. Description of the Background Art
One conventional solution for providing fault tolerance in digital processing by central processing units (CPUs) involves a computer system with multiple CPUs. For example, the multiple CPUs may be operated in full lock-step to achieve a level of fault-tolerance in their computations. Such lock-stepping may be implemented using highly complex voting schemes. Substantial extra system hardware is required (for example, typically three times that needed for a non-redundant solution). Hence, the lock-step solution disadvantageously requires additional system hardware and support infrastructure.
Another conventional solution for providing fault tolerance in digital processing by central processing units (CPUs) involves the use of software verification. The software verification may be performed either by executing the program multiple times on the same computer or on different computers. Typically, the program is re-run at least three times, resulting in effective execution times that are three times greater than they are without the software verification. As such, the software-verification solution disadvantageously requires a longer run-time or requires multiple computers.
Another conventional solution is to perform system self-test or off-line diagnostics. Such testing may provide quality verification of CPU execution units. However, the computer system needs to be shut down to run these programs. This requires undesirable system downtime.
The above-discussed conventional solutions are expensive in terms of cost and/or system performance. Hence, improvements in systems and methods for providing fault tolerant digital processing by CPUs are highly desirable.